1. Field of the Invention
This invention relates to non-volatile memory arrays and, more particularly, to apparatus for helping such arrays to switch at faster rates.
2. History of the Prior Art
There are a number of types of non-volatile memory arrays utilized to store digital information. Erasable read only memory (EPROM) and extensions of EPROM are used for many purposes. In general, such arrays are comprised of many transistors arranged in rows and columns with selection circuitry for determining the particular transistors to access. There has been a general tendency for such arrays (as for all memory arrays) to grow larger by including more and more memory transistors. As the number of transistors in a memory array connected to any selection line (such as a wordline or bitline) increases so does the capacitance affecting the line. This has the general tendency of slowing the rate at which switching can be accomplished. At the same time that the number of transistors in memory arrays is growing larger, the size of the individual transistor devices is growing smaller. Consequently, along with this increase in capacitance has come a reduction of the current which can be transferred by the individual memory devices and a consequent slowing of the switching. Since the smaller transistors cannot transfer as much current, charging the capacitance of any selection line takes longer. These twin tendencies associated with the growth of the size of memory arrays have the effect of slowing the ability of the selection circuitry to switch between memory positions.